The present invention relates to techniques and circuits for providing a plurality of clock signals to a programmable logic device, and more particularly, providing clock signals that are adjustable in phase relative to an input clock signal.
Generally, programmable logic devices (PLD) such as field programmable gate arrays (FPGA), include thousands of programmable logic cells that use combinations of logic gates and/or look-up tables (LUTs) to perform a logic operation. Programmable devices also include a number of functional blocks having specialized logic devices adapted to specific logic operations, such as adders, multiply and accumulate circuits, phase-locked loops (PLL), and memory. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
PLDs utilize internal and external clock signals for operation. For example, a FPGA may accept an internal or external “reference” clock signal that is then used to synchronize the operation of the internal FPGA circuitry. As integrated circuits shrink, and clock speeds increase, providing a clock signal capable of synchronization the circuitry of a PLD becomes increasingly problematic. Propagation delays due to internal buffering and interconnection routing causes the clock signal to become skewed leading to an increase in PLD operational errors.
Some circuit elements of the PLD, such as combinational logic, may be employed to statically delay clock signals. The static delay is used to adjust the phase of the clock signal from an input location to an output location on the PLD. The static delay is used to align the phase between the output clock signal and the reference clock signal. Unfortunately, such static delay may dramatically change over the PLD operating range eliciting operational errors, and using such circuit elements wastes valuable PLD resources.
There is therefore a need for circuits and methods to provide a simple and cost effective circuit that provides an adjustable phase output for one or more output clock signals.